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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 0.5 / jul. 2007 1 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 512mb nand flash hy27us(08/16)12(1/2)b hy27us0812(1/2)b hy27us1612(1/2)b
rev 0.5 / jul. 2007 2 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash document title 512mbit (64mx8bit / 32mx16 bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. oct. 19. 2006 preliminary 0.1 1) correct figure 14 & 15 mar. 07. 2007 0.2 1) add ac characteristics - trb : last re high to busy (at sequential read) - tcry : ce high to ready (in case of interception by ce at read) - tceh : ce high hold time (at the last serial read) mar. 26. 2007 0.3 1) add sequential row read feature and figure 2) modify block replacement apr. 27. 2007 0.4 1) add x16 characteristics 2) modify read2 operation (sequential row read) 3) add ac characteristics - toh : re or ce high to output hold may. 29. 2007 0.5 1) correct read id table 16 2) correct system interface using ce don?t care operation 3) correct command set table 5 jul. 20. 2007
rev 0.5 / jul. 2007 3 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 or x16 bus width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - vcc = 2.7 to 3.6v : hy27us(08/16)12(1/2)b memory cell array x8 : (512+16) bytes x 32 pages x 4,096 blocks x16 : (256+8) words x 32 pages x 4,096 blocks page size - x8 device : (512+16) bytes : hy27us0812(1/2)b - x16 device : (256+8) words : hy27us1612(1/2)b block size - x8 device: (16k + 512 spare) bytes - x16 device: (8k + 256 spare) words page read / program - random access: 12us (max.) - sequential access: 30ns (min.) - page program time: 200us (typ.) copy back program mode - fast page copy without external buffering fast block erase - block erase time: 2ms (typ.) status register electronic signature - 1st cycle: manufacturer code - 2nd cycle: device code chip enable don?t care - simple interface with microcontroller hardware data protection - program/erase locked during power transitions ce don?t card option only data retention - 100,000 program/erase cycles (with 1bit/512byte ecc) - 10 years data retention package - hy27us(08/16)12(1/2)b-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27us(08/16)12(1/2)b-t (lead) - hy27us(08/16)12(1/2)b-tp (lead free) - hy27us0812(1/2)b-s(p) : 48-pin usop1 (12 x 17 x 0.65 mm) - hy27us0812(1/2)b-s (lead) - hy27us0812(1/2)b-sp (lead free) - hy27us0812(1/2)b-f(p) : 63-ball fbga (9 x 11 x 1.0 mm) - hy27us0812(1/2)b-f (lead) - hy27us0812(1/2)b-fp (lead free)
rev 0.5 / jul. 2007 4 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 1. summary description the hynix hy27us(08/16)12(1/2)b series is a 64mx8bit with sp are 2mx8 bit capacity. the device is offered in 3.3v vcc power supply. their nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased independently so it is po ssible to preserve valid data while old data is erased. the memory contains 4096 blocks, composed by 32 pages consis ting in two nand structures of 16 series connected flash cells. a program operation allows to write the 512-byte (x8 device) or 256-word (x16 device) page in typical 200us and an erase operation can be performed in typica l 2ms on a 16k-byte (x8 device) block. data in the page can be read out at 30ns cycle time (3.3v devi ce) per byte. the i/o pins serve as the ports for address and data input/output as well as command in put. this interface allows a reduced pin count and easy migration towards differ- ent densities, without any rearrangement of footprint. commands, data and addresses are synchronously introduced using ce , we , ale and cle input pin. the on-chip program/erase controller automates all progra m and erase functions includ ing pulse repetition, where required, and internal verifica tion and margining of data. the modify operations can be locked using the wp input pin . the output pin r/b (open drain buffer) signals the stat us of the device during each operation. in a system with multiple memories the r/b pins can be connected all together to provide a global status signal. even the write-intensive systems can take advantage of th e hy27us(08/16)12(1/2)b extended reliability of 100k pro- gram/erase cycles by providing ecc (error correc ting code) with real time mapping-out algorithm. the chip is offered with the ce don?t care function. this option allows the di rect download of the code from the nand flash memory device by a microcontroller, since the ce transitions do not stop the read operation. the copy back function allows the optimi zation of defective blocks management: when a page program operation fails the data can be directly programmed in anot her page inside the same array section without the time consuming serial data insertion phase. this device includes also extra features like otp/unique id area, read id2 extension. the hy27us(08/16)12(1/2)b is available in 48 - tsop1 12 x 20 mm package, 48 - usop1 12 x 17 mm, fbga 9 x 11 mm. 1.1 product list part number orization vcc range package hy27us0812(1/2)b x8 2.7v - 3.6 volt 48tsop1/ 48usop1/ 63fbga hy27us1612(1/2)b x16 48tsop1
rev 0.5 / jul. 2007 5 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 9&& 966 :3 &/( $/( 5( :( &( ,2a,2 ,2a,2[rqo\ 5% figure1: logic diagram io15 - io8 data input / outputs (x16 only) io7 - io0 data inputs / outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect r/b ready / busy vcc power supply vss ground nc no connection table 1: signal names
rev 0.5 / jul. 2007 6 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 2. 48tsop1 contac tions, x8 and x16 device 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 8623 [ 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 9vv ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 1& 9ff 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9vv 1$1')odvk 7623 [ 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [ figure 3. 48usop1 contactions, x8
rev 0.5 / jul. 2007 7 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 1& 1& 1& 1& 1& 1& 1& 1& &/( $/( 9vv 9vv 9vv 9ff 9ff 1& 1& 1& :3 5( &( :( 5% 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& $ % & ' ( ) * + - . / 0 figure 4. 63fbga contactions, x8 device (top view through package)
rev 0.5 / jul. 2007 8 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 1.2 pin description pin name description io0-io7 io8-io15(1) data inputs/outputs the io pins allow to input comma nd, address and data and to outp ut data during read / program operations. the inputs are latched on the rising edge of write enable (we ). the i/o buffer float to high-z when the device is deselected or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the command register on the rising edge of write enable (we ). ale address latch enable this input activates the latching of the io inputs inside the address register on the rising edge of write enable (we ). ce chip enable this input controls the selection of th e device. when the device is busy ce low does not deselect the memory. we write enable this input acts as clock to latch command, addre ss and data. the io inputs are latched on the rise edge of we . re read enable the re input is the serial data-out co ntrol, and when active drives th e data onto the i/o bus. data is valid trea after the falling edge of re which also increments the inte rnal column address counter by one. wp write protect the wp pin, when low, provides an hardware protection against undesired modify (program / erase) operations. r/b ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all the operations (read, write, erase). vss ground nc no connection table 2: pin description note: 1. for x16 version only 2. a 0.1uf capacitor should be connected between the vcc supply voltage pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations.
rev 0.5 / jul. 2007 9 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a9 a10 a11 a12 a13 a14 a15 a16 3rd cycle a17 a18 a19 a20 a21 a22 a23 a24 4th cycle a25 l (1) l (1) l (1) l (1) l (1) l (1) l (1) table 3: address cycle map(x8) note: 1. l must be set to low. 2. a8 is set to low or high by the 00h or 01h command. io0 io1 io2 io3 io4 io5 io6 io7 io8-io15 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 l (1) 2nd cycle a9 a10 a11 a12a13a14a15a16 l (1) 3rd cycle a17 a18 a19 a20 a21 a22 a23 a24 l (1) 4th cycle a25 l (1) l (1) l (1) l (1) l (1) l (1) l (1) l (1) table 4: address cycle map(x16) note: 1. l must be set to low. function 1st cycle 2nd cycle 3rd cycle 4th cycle acceptable command during busy read 1 00h/01h - - - read 2 50h--- read id 90h--- reset ffh - - - yes page program (start) 80h 10h - - copy back pgm (start) 00h 8ah - - block erase 60h d0h - - read status register 70h--- yes table 5: command set
rev 0.5 / jul. 2007 10 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash cle ale ce we re wp mode h l l rising h x read mode command input l h l rising h x address input(4 cycles) h l l rising h h write mode command input l h l rising h h address input(4 cycles) lllrisinghhdata input ll l (1) h falling x sequential read and data output l l l h h x during read (busy) xxxxxhduring program (busy) xxxxxhduring erase (busy) xxxxxlwrite protect xxhxx0v/vccstand by table 6: mode selection note: 1. with the ce high during latency time does not stop the read operation
rev 0.5 / jul. 2007 11 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 2. bus operation there are six standard bus operations that control the devi ce. these are command input, address input, data input, data output, write protect, and standby. typically glitches less than 5 ns on chip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 2.1 command input. command input bus operation is used to give a command to the memory device. command are accepted with chip enable low, command latch enable high, address latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify operation (write/erase) the write protect pin must be high. see figure 6 and table 13 for details of the ti mings requirements. command codes are always applied on io7:0, disregarding the bus configuration (x8/x16). 2.2 address input. address input bus operation allows the insertion of the memo ry address. to insert the 25 addresses needed to access the 512mbit 4 clock cycles (x8 version) are needed. addresses are accepted with chip enable low, address latch enable high, command latch enable low and read enable high and latched on the rising edge of write enable. more- over for commands that starts a modify operation (write/era se) the write protect pin must be high. see figure 7 and table 13 for details of the timings requirements. addresses ar e always applied on io7:0, disregarding the bus configu- ration (x8/x16). 2.3 data input. data input bus operation allows to feed to the device the data to be programm ed. the data insertion is serially and timed by the write enable cycles. data are accepted only wi th chip enable low, addre ss latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 8 and table 13 for details of the timings requirements. 2.4 data output. data output bus operation allows to read data from the me mory array and to check the st atus register content, the lock status and the id data. data can be serially shifted ou t toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latch en able low. see figures 9 to 15 and table 13 for details of the timings requirements. 2.5 write protect. hardware write protection is activated when the write protec t pin is low. in this condition modify operation do not start and the content of the memory is not altered. write pr otect pin is not latched by wr ite enable to ensure the pro- tection even during the power up. 2.6 standby. in standby mode the device is deselected, output s are disabled and power consumption is reduced.
rev 0.5 / jul. 2007 12 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 3. device operation 3.1 page read. three types of operations are available: random read, serial page read and sequential row read. the random read mode is enabled when the page addre ss is changed. the 528 bytes (x8 device) or 264 words (x16 device) of data within the sele cted page are transferred to the data regist ers in less than access random read time tr (12us). the system controller can detect the completion of th is data transfer tr (12us) by analyzing the output of r/b pin. once the data in a page is loaded into the registers, they may be read out in 30ns cycle time by sequentially puls- ing re . high to low transitions of the re clock output the data stating from the selected column address up to the last column address. after the data of last column address is clocked out, the next page is automati cally selected for sequential row read. waiting tr again allows reading the selected page. the sequ ential row read operation is terminated by bringing ce high. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. writing the read2 command user may selectively access the spare area of bytes 512 to 527 (x8 device) or words 256 to 263 (x16 device). addresses a0 to a3 set the starting address of the spare area while addresses a4 to a7 are ignored. unless the operation is aborted, the page addre ss is automatically incremented for sequential row read as in read1 operation and spare sixteen bytes of each page (x8 device) or eight words of each page (x16 device) may be sequentially read. the read1 command (00h/01h) is needed to move the pointer back to the main area. the read2 command (50h) is needed to mo ve the pointer back to the spare area. figure_11 to 14 show typical sequence and timings for each read operation. 3.2 page program. the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 (x8 device), in a single page program cycle. the number of consecutive partial page pro- gramming operations within the same pa ge without an intervening erase operation must not exceed 1 for main array and 2 for spare array. the addressing may be done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes (x8 devi ce) or 264 word (x16 device) of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. serial data loading can be started from 2nd half array by moving pointer. about the pointer operation, please refer to figure 24 the data-loading sequence begi ns by inputting the serial data input command (80h), fol- lowed by the four address input cycles and then serial da ta loading. the page program confirm command (10h) starts the programming process. writing 10h alone without previously entering the serial data will not initiate the program- ming process. the internal program eras e controller automatically executes th e algorithms and timings necessary for program and verify, thereby freeing the system controller fo r other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status regi ster. the system controller can detect the completion of a prog ram cycle by monitoring the r/b output, or the status bit (i/o 6) of the status register. only the read status command and reset command are vali d while programming is in progress. when the page pro- gram is complete, the write status bit (i/o 0) may be checked in figure 15 the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. th e command register remains in read status command mode until another valid command is wr itten to the command register.
rev 0.5 / jul. 2007 13 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 3.3 block erase. the erase operation is done on a block (16k byte) basis. it consists of an erase setup command (60h), a block address loading and an erase confirm command (d0h). the erase confirm command (d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setu p followed by execution com- mand ensures that memory contents are not accidentally erased due to external noise conditions. the block address loading is accomplished three cycles. only block addresses (a 14 to a25 , highest address depending on the device density) are needed while a9 to a13 is ignored. at the rising edge of we after the erase confirm command input, the in ternal program erase controller handles erase and erase-verify. when the erase operation is completed, th e write status bit (i/o 0) may be checked. figure 17 details the sequence. 3.4 copy-back program. the copy-back program is provided to quickly and efficientl y rewrite data stored in one page within the plane to another page within the same plane wi thout using an external memory. since the time-consuming sequential reading and its reloading cycles are removed, the system performance is improved. the benefit is especially obvious when a portion of a block is upda ted and the rest of the block also need to be copied to the newly assigned free block. the operation for performing a copy-back progra m is a sequential execution of page-read without burst- reading cycle and copying-program with the address of de stination page. a normal read operation with "00h" com- mand and the address of the source page moves th e whole 528byte data into the internal buffer. as soon as the device returns to ready state, page-copy da ta-input command (8ah) with the address cycles of desti- nation page followed may be written. the program confir m command (10h) is not needed to actually begin the pro- gramming operation. for backward-compa tibility, issuing program confirm command during copy-back does not affect correct device operation. copy-back program operation is allowed only within the same memory plane. once the co py-back program is finished, any additional partial page programming into the copied pages is prohibited be fore erase. plane address must be the same between source and target page. "when there is a program-failure at copy-back operation, erro r is reported by pass/fail status. but, if copy-back oper- ations are accumulated over time, bit error due to charge lo ss is not checked by external error detection/correction scheme. for this reason, two bit error correction is recommended for the use of copy-back operation." figure 16 shows the command sequ ence for the copy-back operation. the copy back program operation requires three steps: 1. the source page must be read using the read a co mmand (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). th is operation copies all 2kbytes from the page into the page buffer. 2. when the device returns to the ready state (ready/b usy high), the second bus write cycle of the command is given with the 4bus cycles to input the target page address. the value for a25 from second to the last page address must be same as the value given to a25 in first address. 3. then the confirm command is issu ed to start the p/e/r controller.
rev 0.5 / jul. 2007 14 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 3.5 read status register. the device contains a status register which may be read to find out whether read, program or erase operatio is com- pleted, and whether the read, program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle outputs the content of the st atus register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two-line control allows the syst em to poll the progress of each device in multiple mem- ory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 14 for specific status register definitions. the command register remains in status read mode until fur- ther commands are issued to it. therefore, if the status regi ster is read during a random read cycle, a read command (00h or 50h) should be given before sequential page read cycle. 3.6 read id. the device contains a product identification mode, initiate d by writing 90h to the command register, followed by an address input of 00h. four read cycles sequentially output the 1st cycle (adh), and 2nd cycle (the device code) and 3rd cycle id, 4th cycle id, respectively. the command regist er remains in read id mode until further commands are issued to it. figure 18 shows the operation se quence, while tables 16 explain the byte meaning. 3.7 reset. the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operat ion will abort these operatio ns. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next comman d, and the status register is cleared to value c0h when wp is high. refer to table 14 for device status after reset op eration. if the device is already in reset state a new reset command will not be accepted by the command register. the r/b pin transitions to low for trst after the reset com- mand is written. refer to figure 21 below.
rev 0.5 / jul. 2007 15 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 4. other features 4.1 data protection fo r power on/off sequence the device is designed to offer protection from any involu ntary program/erase during powe r-transitions. an internal voltage detector disables all functions whenev er vcc is below about 2.0v(3.0v device). wp pin provides hardware pro- tection and is recommended to be kept at vil during power-up an d power-down. a recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in figure 22. the two-step command sequence for program/erase provides additional software protection. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the co mpletion of a page program, erase, copy-back and random read completion. the r/b pin is normally high and goes to lo w when the device is busy (after a reset, read, program, erase operation). it returns to high wh en the internal controller ha s finished the operation. the pin is an open-drain driver th ereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart in figure 23. its value can be determined by the following guidance.
rev 0.5 / jul. 2007 16 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash parameter symbol min typ max unit valid block number n vb 4016 4096 blocks table 7: valid blocks number note: 1. the 1st block is guaranteed to be a valid bl ock up to 1k cycles with ecc. (1bit/528bytes) symbol parameter value unit 3.3v t a ambient operating temperature (temperature range option 1) 0 to 70 ambient operating temperature (industrial temperature range) -40 to 85 t bias temperature under bias -50 to 125 t stg storage temperature -65 to 150 v v io (2) input or output voltage -0.6 to 4.6 v vcc supply voltage -0.6 to 4.6 v table 8: absolute maximum ratings note: 1. except for the rating ?operating temperature range?, stresses above those listed in the table ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. minimum voltage may undershoot to -2v during tr ansition and for less than 20ns during transitions.
rev 0.5 / jul. 2007 17 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 5: block diagram $''5(66 5(*,67(5 &2817(5 352*5$0 (5$6( &21752//(5 +9*(1(5$7,21 &200$1' ,17(5)$&( /2*,& &200$1' 5(*,67(5 '$7$ 5(*,67(5 ,2 5( %8))(56 <'(&2'(5 3$*(%8))(5 ; ' ( & 2 ' ( 5 0elw 0elw 1$1')odvk 0(025<$55$< :3 &( :( &/( $/( $a$
rev 0.5 / jul. 2007 18 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash parameter symbol test conditions 3.3volt unit min typ max operating current sequential read i cc1 t rc =30ns ce =v il , i out =0ma -1530ma program i cc2 - - 15 30 ma erase i cc3 - - 15 30 ma stand-by current (ttl) i cc4 ce =v ih , wp =0v/vcc -- 1ma stand-by current (cmos) i cc5 ce =vcc-0.2, wp =0v/vcc -1050ua input leakage current i li v in= 0 to vcc (max) - - 10 ua output leakage current i lo v out =0 to vcc (max) - - 10 ua input high voltage v ih - vccx0.8 - vcc+0.3 v input low voltage v il --0.3-vccx0.2v output high voltage level v oh i oh =-400ua 2.4 - - v output low voltage leve v ol i ol =2.1ma - 0.4 v output low current (r/b ) i ol (r/b ) v ol =0.4v 8 10 - ma table 9: dc and operating characteristics parameter value 3.3volt input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc / 2 output load (2.7v - 3.6v) 1 ttl gate and cl=50pf table 10: ac conditions
rev 0.5 / jul. 2007 19 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash item symbol test condition min max unit input / output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf table 11: pin capacita nce (ta=25c, f=1.0mhz) parameter symbol min typ max unit program time t prog - 200 700 us number of partial program cycles in the same page main array nop - - 1 cycles spare array nop - - 2 cycles block erase time t bers -23ms table 12: program / erase characteristics
rev 0.5 / jul. 2007 20 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash parameter symbol 3.3v olt unit min max cle setup time t cls 15 ns cle hold time t clh 5ns ce setup time t cs 20 ns ce hold time t ch 5ns we pulse width t wp 15 ns ale setup time t als 15 ns ale hold time t alh 5ns data setup time t ds 15 ns data hold time t dh 5ns write cycle time t wc 30 ns we high hold time t wh 10 ns data transfer from cell to register t r 12 us ale to re delay t ar 10 ns cle to re delay t clr 10 ns ready to re low t rr 20 ns re pulse width t rp 15 ns we high to busy t wb 100 ns read cycle time t rc 30 ns re access time t rea 18 ns re high to output high z t rhz 50 ns ce high to output high z t chz 50 ns re or ce high to output hold t oh 10 ns re high hold time t reh 10 ns output high z to re low t ir 0ns ce access time t cea 25 ns we high to re low t whr 60 ns last re high to busy (at sequential read) t rb 100 ns ce high to ready (in case of interception by ce at read) t cry 60+tr(r/b#) (4) ns ce high hold time (at the last serial read) (3) t ceh 100 ns device resetting time (read / program / erase) t rst 5/10/500 (1,2) us write protection time t ww (5) 100 ns table 13: ac timing characteristics note: 1. if reset command (ffh) is wr itten at ready state, the device goes into busy for maximum 5us 2. the time to ready depends on the va lue of the pull-up resistor tied r/b pin.ting time. 3. to break the sequential read cycle, ce must be held for longer time than tceh. 4. the time to ready depends on the va lue of the pull-up resistor tied r/b pin. 5. program / erase enable operation : wp high to we high. program / erase disable operation : wp low to we high.
rev 0.5 / jul. 2007 21 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash io pagae program block erase read cache read coding 0 pass / fail pass / fail na pass: ?0? fail: ?1? 1na na na pass: ?0? fail: ?1? (only for cache program, else don?t care) 2na na na - 3na na na - 4na na na - 5 ready/busy ready/busy ready/busy p/e/r controller bit active: ?0? idle: ?1? 6 ready/busy ready/busy ready/busy ready/busy busy: ?0? ready?: ?1? 7 write protect write protect write protect protected: ?0? not protected: ?1? table 14: status register coding deviidentifier cycle description 1st manufacturer code 2nd device identifier table 15: device identifier coding part number voltage bus width 1st cycle (manufacture code) 2nd cycle (device code) hy27us0812(1/2)b 3.3v x8 adh 76h hy27us1612(1/2)b 3.3v x16 adh 56h table 16: read id data table
rev 0.5 / jul. 2007 22 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 6: command latch cycle w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2[ w'+ w'6 w$/6 w$/+ w&/+ w&+ w&/6 w&6 w:3 w:& w:& w:3 w:3 w:3 w$/6 w:+ w:+ w:+ w$/+ w$/6 w$/6 w$/6 &ro$gg w$/+ w$/+ w$/+ w'+ &ro$gg 5rz$gg 5rz$gg w:& w'+ w'+ w'+ w'6 w'6 w'6 w'6 &/( &( :( $/( ,2[ figure 7: address latch cycle
rev 0.5 / jul. 2007 23 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash w:& w$/6 w&/+ w&+ w:3 w:+ ',1 ',1 ',1ilqdo w'+ w'+ w'+ w'6 w'6 w'6 w:3 w:3 &/( $/( &( ,2[ :( t cea t rea t rp t rea t rhz t rhz* dout dout dout t chz* t oh t oh t rea t reh t rc t rr notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. ce re r/b i/ox figure 9: sequential out cycle after read (cle=l, we =h, ale=l) figure 8. in put data latch cycle
rev 0.5 / jul. 2007 24 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 10: status read cycle t cls t clr t clh t cs t ch t wp t whr t cea t ds t rea t chz t rh = t 2 h t 2 h 70h status output t dh t ir ce we i/o x cle re &/( &( :( $/( 5( ,2 [ 5% w:& w&(+ w&+= w&5< w5+= w5& w5 w$5 w:% w53 kruk &ro$gg 5rz$gg 5rz$gg 5rz$gg 'rxw1 'rxw1 'rxw1 'rxw w5% &roxpq $gguhvv 3djh5rz$gguhvv %xv\ figure 11: read1 operation (read one page)
rev 0.5 / jul. 2007 25 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash &/( &( :( $/( 5( ,2[ 5% kruk &ro$gg 5rz$gg 5rz$gg 5rz$gg 'rxw1 'rxw1 'rxw1 %xv\ w55 w5 w5& w$5 w:% w&+= &ro$gg 5rz$gg figure 12: read1 operation intercepted by ce &/( &( :( $/( 5( ,2[ 5% k &ro$gg 5rz$gg 5rz$gg 'rxw 1 'rxw 1 'rxw 'rxw 0 2xwsxw 1 2xwsxw 0 %xv\ %xv\ 5hdg\ 5rz$gg figure 13: read2 operation (sequential row read)
rev 0.5 / jul. 2007 26 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash &/( $/( &( 5( 5% ,2[ :( w:& k &ro$gg 6huldo'dwd ,qsxw&rppdqg &roxpq $gguhvv 5rz$gguhvv 5hdg6wdwxv &rppdqg 3urjudp &rppdqg ,2r 6xffhvvixo3urjudp ,2r (uurulq3urjudp [xswr%\wh [xsws:rug 6huldo,qsxw 5rz$gg 5rz$gg 'lq 1 'lq 0 k k ,2r w:& w:& w:% w352* 5rz$gg &/( &( :( $/( 5( ,2[ 5% k &ro$gg 5rz$gg 5rz$gg 'rxw 1 'rxw 1 'rxw 'rxw 'rxw 'rxw 0 1 2xwsxw 0 2xwsxw %xv\ %xv\ 5hdg\ 5rz$gg figure 15: page program operation figure 14: sequential row re ad operation within a block
rev 0.5 / jul. 2007 27 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash w:& w:% w5 w352* ,2 k $k k &ropq $gguhvv 5rz$gguhvv &ropq $gguhvv 5rz$gguhvv 5hdg6wdwxv &rppdqg %xv\ %xv\ ,2 6xffhvvixo3urjudp ,2 (uurulq3urjudp &rs\%dfn'dwd ,qsxw&rppdqg kzulwhf\fohqrpruh &/( &( :( $/( 5( ,2 [ 5% &ro$gg 5rz$gg 5rz$gg 5rz$gg &ro$gg 5rz$gg 5rz$gg 5rz$ gg figure 16 : copy back program
rev 0.5 / jul. 2007 28 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash w:& &/( &( :( $/( 5( ,2 [ 5% w:% w%(56 %86< k ,2 5rz$gg 5rz$gg 5rz$gg k $xwr%orfn(udvh6hwxs&rppdqg (udvh&rppdqg 5hdg6wdwxv &rppdqg ,2 6xffhvvixo(udvh ,2 (uurulq(udvh 5rz$gguhvv 'k figure 17: block erase op eration (erase one block) tar 90h cle ce we ale re i/o x 00h trea read id command address 1 cycle maker code device code adh k figure 18: read id operation
rev 0.5 / jul. 2007 29 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash system interface using ce don?t care to simplify system interface, ce may be deasserted during data loading or sequential data-reading as shown below. so, it is possible to connect nand flas h to a microporcessor. the only function that was removed from standard nand flash to make ce don?t care read operation was disabling of the au tomatic sequential read function. (hy27us(08/16)122b) &(grq?wfduh k 6wduw$gg&\foh 'dwd,qsxw k 'dwd,qsxw &/( &( :( $/( ,2[ figure 19: program operation with ce don?t-care. ,ivhtxhqwldourzuhdghqdeohg &(pxvwehkhogorzgxulqjw5 &(grq?wfduh k k &/( &( 5( $/( 5% :( ,2[ 6wduw$gg&\foh 'dwd2xwsxwvhtxhqwldo w5 figure 20: read operation with ce don?t-care.
rev 0.5 / jul. 2007 30 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 21: reset operation ))k w 567 :( $/( &/( 5( ,2 5% :3 :( 9ff xv w 9 7+ figure 22: power on and data protection timing vth = 2.5 volt for 3.3 volt supply devices
rev 0.5 / jul. 2007 31 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash 5sydoxhjxlghqfh 5splq zkhuh,/lvwkhvxpriwkhlqsxwfxuuqwvridooghylfhvwlhgwr wkh5%slq 5spd[lvghwhuplqhge\pd[lpxpshuplvvleoholplwriwu #9ff 97d ?&& / s) )lj5syvwuwi 5syvlexv\ 9ff0d[9 2/ 0d[ 9 p$?, / , 2/ ?, / 5s lexv\ 5srkp lexv\ lexv\>$@ wuwi>v@ wi %xv\ 5hdg\ 9ff 9 2+ 9 2/ 9 99 9 2/ 2+ wu wi 9ff q p n n n n q p q p *1' 'hylfh rshqgudlqrxwsxw 5% figure 23: ready/busy pin electrical specifications
rev 0.5 / jul. 2007 32 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash ['hylfhv $uhd$ k $uhd% k $uhd& k %\whv %\whv %\whv $%& 3rlqwhu kkk 3djh%xiihu ['hylfhv $uhd$ k $uhd& k %\whv %\whv $& 3rlqwhu kk 3djh%xiihu k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k k k $gguhvv ,qsxwv 'dwd,qsxw k $5($$ $5($% $5($& ,2 ,2 ,2 $uhdv$%&fdqehsurjudpphgghshqglqjrqkrzpxfkgdwdlvl qsxw6xevhtxhqwkfrppdqgvfdqehrplwwhg $uhdv%&fdqehsurjudpphgghshqglqjrqkrzpxfkgdwdlvlqsx w7khkfrppdqgpxvwehuhlvvxhgehiruhhdfksurjudp 2qo\$uhdv&fdqehsurjudpphg6xevhtxhqwkfrppdqgfdqehr plwwhg figure 24: pointer operations figure 25: pointer operations for porgramming
rev 0.5 / jul. 2007 33 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash bad block management devices with bad blocks have the same quality level and th e same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations inside valid blocks erased(ffh). the bad block information is written prior to shipping. any block where the 6th byte/ 3rd word in the spare area of the 1st or 2nd page (if the 1st page is bad) does not cont ain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recog- nize the bad blocks based on the original information it is recomme nded to create a bad block table following the flow- chart shown in figure 26. the 1st block, which is placed on 00h block address is guar anteed to be a valid block. block replacement over the lifetime of the device additional bad blocks may develop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. as the failure of a page program operation does not affect th e data in other pages in the same block, the block can be replaced by re-programming the current data and copying th e rest of the replaced block to an available valid block. the copy back program command can be us ed to copy the data to a valid block. see the ?copy back program? section for more details. refer to table 18 for the recommended procedure to follow if an error occurs during an operation . operation recommended procedure erase block replacement program block replacement read ecc (with 1bit/528byte) figure 26: bad block management flowchart <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh table 18: block failure
rev 0.5 / jul. 2007 34 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash write protect operation the erase and program operations are automatically reset when wp goes low (tww = 100ns, min). the operations are enabled and disabled as follows (figure 27~30) :: w k k :( ,2[ :3 5% k k w :: :( ,2[ :3 5% figure 27: enable programming figure 28: disable programming
rev 0.5 / jul. 2007 35 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash k w 'k :: :( ,2[ :3 5% k w :: 'k :( ,2[ :3 5% figure 29: enable erasing figure 30: disable erasing
rev 0.5 / jul. 2007 36 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash table 19: 48pin-tsop1, 12 x 20mm, package mechanical data symbol millimeters min typ max a 1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.100 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e 0.500 l 0.500 0.680 alpha 0 5 ' $ ',( $ h % / . ( ( & &3 $ figure 31: 48pin-tsop1, 12 x 20mm, package outline
rev 0.5 / jul. 2007 37 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash symbol millimeters min typ max a 0.650 a1 0 0.050 0.080 a2 0.470 0.520 0.570 b 0.130 0.160 0.230 c 0.065 0.100 0.175 c 1 0.450 0.650 0.750 cp 0.100 d 16.900 17.000 17.100 d1 11.910 12.000 12.120 e 15.300 15.400 15.500 e 0.500 alpha 0 8 figure 32. 48pin-us op1, 12 x 17mm, package outline table 20: 48pin-usop1, 12 x 17 mm, package mechanical data $ $ $ & ' ( & h % $qjoh doskd ' . &3
rev 0.5 / jul. 2007 38 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash symbol millimeters min typ max a 0.80 0.90 1.00 a1 0.25 0.30 0.35 a2 0.55 0.60 0.65 b 0.40 0.45 0.50 d 8.90 9.00 9.10 d1 4.00 d2 7.20 e 10.90 11.00 11.10 e1 5.60 e2 8.80 e0.80 fd 2.50 fd1 0.90 fe 2.70 fe1 1.10 sd 0.40 se 0.40 $ $ $ 6( )( )( h ( ( %$//3 fs ( h h e ' ' 6' )' )' ' figure 33. 63-ball fbga - 9 x 11 ball array 0.8mm pitch, pakage outline note : drawing is not to scale.
rev 0.5 / jul. 2007 39 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash marking information - tsop1/usop packag marking example tsop1 / usop k o r h y 2 7 u s x x 1 2 x b x x x x y w w x x - hynix - kor - hy27usxx12xb xxxx hy: hynix 27: nand flash u: power supply s: classification xx: bit organization 12: density x: mode b: version x: package type x: package material x: operating temperature x: bad block - y: year (ex: 5=year 2005, 06= year 2006) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix symbol : origin country : u(2.7v~3.6v) : single level cell+single die+sm all block : 08(x8), 16(x16) : 512mbit : 1nce & 1r/nb; sequential row read enable : 1nce & 1r/nb; sequential row read disable : 3rd generation : t(48-tsop1), s(48-usop) : blank(normal), p(lead free) : c(0 ~70 ), i(-40 ~85 ) : b(included bad block), s(1~5 bad block), p(all good block) : fixed item : non-fixed item : part number
rev 0.5 / jul. 2007 40 hy27us(08/16)12(1/2)b series 512mbit (64mx8bit / 32 mx16bit) nand flash marking information - fbga packag marking example fbga k o r h y 2 7 u s 0 8 1 2 x b x x x x y w w x x - hynix - kor - hy27u0812xb xxxx hy: hynix 27: nand flash u: power supply s: classification 08: bit organization 12: density x: mode b: version x: package type x: package material x: operating temperature x: bad block - y: year (ex: 5=year 2005, 06= year 2006) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix symbol : origin country : u(2.7v~3.6v) : single level cell+single die+sm all block : 08(x8) : 512mbit : 1nce & 1r/nb; sequential row read enable : 1nce & 1r/nb; sequential row read disable : 3rd generation : f(63fbga) : blank(normal), p(lead free) : c(0 ~70 ), i(-40 ~85 ) : b(included bad block), s(1~5 bad block), p(all good block) : fixed item : non-fixed item : part number

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